GeekRadar / The comparison desk

COMPARE.

CPU

TI TMS99110AJDL

Processor

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 35 fields

Address bus declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Architecture declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Component type

CPU^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Clone designation

no^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core design

TMS99110^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Declared processor cores

1^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core designer

TI^*

Scope and conditions

Package: Side-brazed CDIP-40^*

External data bus declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Family

TMS99000^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Floating-point unit declaration

Single-precision instructions are emulated by Macrostore feature^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: Side-brazed CDIP-40^*

External clock declaration

24^* MHz

Scope and conditions

Package: Side-brazed CDIP-40^*

Maximum or typical clock declaration

6^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: Side-brazed CDIP-40^*

Initial price declaration

Amount: 99^*
Currency: USD^*

Scope and conditions

Price scope: Initial price; market unspecified^*
Package: Side-brazed CDIP-40^*

Instruction-set architecture

TMS9900^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 data cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L2 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L3 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Manufacturer

TI^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip peripherals

Clock generator^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Package

Side-brazed CDIP-40^*

Part number

TMS99110AJDL^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Typical power declaration

0.63^* W

Scope and conditions

Package: Side-brazed CDIP-40^*

Fabrication technology

N-channel silicon-gate SMOS technology^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip RAM declaration

32^* B

Scope and conditions

Condition: Marcostore memory^*
Package: Side-brazed CDIP-40^*

Maximum RAM declaration

64^* KiB

Scope and conditions

Condition: data, 64KiB instruction^*
Package: Side-brazed CDIP-40^*

Release date declaration

Dec-81^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip ROM declaration

1^* KiB

Scope and conditions

Condition: Macrostore memory^*
Package: Side-brazed CDIP-40^*

Socket or package footprint

DIP-40^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature grade

Commercial^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature range declaration

0^* – 70^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: Side-brazed CDIP-40^*

Core supply voltage range

5^* V

Scope and conditions

Condition: +/- 5%^*
Package: Side-brazed CDIP-40^*

Typical core supply voltage

5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

I/O supply voltage

5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

* Provisional data