GeekRadar / The comparison desk

COMPARE.

CPU

Freescale Semiconductor

PowerPC e500

Processor

No matched benchmark results are available for this entry yet.

System configuration

Detailed specifications

Specifications 1 · 6 fields

Family architecture options

Issue width

2^*

Pipeline stages

7^*

L1 instruction

32^* KiB

L1 data

32^* KiB

L2 cache options

256^* KiB
512^* KiB
1,024^* KiB

Clock endpoints

Minimum: 533^* MHz
Maximum: 1.5^* GHz

Core family

Designer: Freescale Semiconductor^*
CPU class: 32-bit^*
Instruction family: PowerPC Book E^*
Versions: e500v1^*
e500v2^*
e500mc^*
Common product family: MPC85xx / PowerQUICC III^*

e500mc architecture

Introduced: 2008-06^*
ISA: Power ISA 2.06^*
Hypervisor/virtualization: Yes^*
Classic FPU: Yes^*
SPE: No^*
SPESFP: No^*
DPESFP: No^*
Integer register width: 32^* bit
Interconnect: CoreNet^*
L2 allocation: Per core^*

Named core successors

Core
e5500^*
Introduced
2,010^*
Word size
64^* bit
Core
e6500^*
Introduced
2,012^*
Multithreading
Yes^*

e500v1 architecture

Extensions: SPE^*
SPESFP^*
SPE register width: 64^* bit
Non-SPE register access width: 32^* bit
Classic FPU: No^*
Floating-point model: Embedded single precision using integer registers; not fully IEEE 754 compliant^*

e500v2 additions

Physical address width: 36^* bit
Physical address space: 64^* GiB
Additional page sizes: 1^* GiB
4^* GiB
Double-precision extension: DPESFP^*
4K-page translation array entries: 512^*
4K-page array associativity: 4^*
Maximum outstanding data-cache misses: 5^*
Alternate Time Base: Yes^*
Scope: Address space, not an installed-memory guarantee^*

Specifications 2 · 1 fields

Manufacturer: Freescale Semiconductor^*

* Provisional data