Freescale Semiconductor

PowerPC e500

Processore

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Configurazione di sistema

Specifiche dettagliate

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Opzioni architetturali della famiglia

Issue width

2^*

Pipeline stages

7^*

L1 instruction

32^* KiB

L1 data

32^* KiB

L2 cache options

• 256^* KiB
• 512^* KiB
• 1.024^* KiB

Clock endpoints

Minimum

533^* MHz

Maximum

1,5^* GHz

Famiglia di core

Designer

Freescale Semiconductor^*

CPU class

32-bit^*

Instruction family

PowerPC Book E^*

Versions

• e500v1^*
• e500v2^*
• e500mc^*

Common product family

MPC85xx / PowerQUICC III^*

Architettura e500mc

Introduced

2008-06^*

ISA

Power ISA 2.06^*

Hypervisor/virtualization

Sì^*

Classic FPU

Sì^*

SPE

No^*

SPESFP

No^*

DPESFP

No^*

Integer register width

32^* bit

Interconnect

CoreNet^*

L2 allocation

Per core^*

Core successivi

• Core

  e5500^*

  Introduced

  2.010^*

  Word size

  64^* bit

• Core

  e6500^*

  Introduced

  2.012^*

  Multithreading

  Sì^*

Architettura e500v1

Extensions

• SPE^*
• SPESFP^*

SPE register width

64^* bit

Non-SPE register access width

32^* bit

Classic FPU

No^*

Floating-point model

Embedded single precision using integer registers; not fully IEEE 754 compliant^*

Funzioni aggiuntive e500v2

Physical address width

36^* bit

Physical address space

64^* GiB

Additional page sizes

• 1^* GiB
• 4^* GiB

Double-precision extension

DPESFP^*

4K-page translation array entries

512^*

4K-page array associativity

4^*

Maximum outstanding data-cache misses

5^*

Alternate Time Base

Sì^*

Scope

Address space, not an installed-memory guarantee^*

Specifiche 2 · 1 campi

Produttore

Freescale Semiconductor^*

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