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COMPARE.
CPUMIPS R5000
Processor
- CPU cores
- 1*
No matched benchmark results are available for this entry yet.
Processing & platform
- CPU cores
- 1*
- Hardware threads per core
- 1*
System configuration
Detailed specifications
Specifications ยท 64 fields
- ifu CPU microarchitecture
- 1*
- metal layers Manufacturing process
- 3*
- lsfu CPU microarchitecture
- 1*
- metal Manufacturing process
- aluminum*
- fpfu CPU microarchitecture
- 1*
- date
- 1996-01-01*
- date
- 1996-01-01*
- date
- 1996-01-01*
- date
- 1996-01-01*
- tfu CPU microarchitecture
- 3*
- vdd nom Manufacturing process
- 3.3*
- clock
- 180*
- clock
- 250*
- clock
- 150*
- clock
- 200*
- max inst decoded CPU microarchitecture
- 2*
- hw nthreadspercore
- 1*
- hw nthreadspercore
- 1*
- hw nthreadspercore
- 1*
- hw nthreadspercore
- 1*
- iwindow CPU microarchitecture
- 2*
- hw ncores
- 1*
- hw ncores
- 1*
- hw ncores
- 1*
- hw ncores
- 1*
- bus width
- 64*
- bus width
- 64*
- bus width
- 64*
- bus width
- 64*
- arch int reg CPU microarchitecture
- 32*
- transistors
- 3.6*
- transistors
- 3.6*
- transistors
- 3.6*
- transistors
- 3.6*
- arch fp reg CPU microarchitecture
- 32*
- die size
- 84*
- die size
- 84*
- die size
- 84*
- die size
- 84*
- total arch reg CPU microarchitecture
- 64*
- vdd low
- 3.3*
- vdd low
- 3.3*
- vdd low
- 3.3*
- vdd low
- 3.3*
- vdd high
- 3.3*
- vdd high
- 3.3*
- vdd high
- 3.3*
- vdd high
- 3.3*
- out of order CPU microarchitecture
- f*
- integrated mc CPU microarchitecture
- f*
- l1i CPU cache configuration
- 32*
- l1i CPU cache configuration
- 32*
- name CPU microarchitecture
- R5000*
- name Processor family
- R5000*
- l1d CPU cache configuration
- 32*
- l1d CPU cache configuration
- 32*
- l2 shared CPU cache configuration
- 2,048*
- l2 shared CPU cache configuration
- 512*
- year Manufacturing process
- 1996*
- technology Manufacturing process
- CMOS*
- feature size Manufacturing process
- 0.35*
- int pipestages CPU microarchitecture
- 5*
- channel length Manufacturing process
- 0.35*
- max uop issued per cycle CPU microarchitecture
- 2*
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* Provisional data