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CPU
MIPS

MIPS R10000

Processor

CPU cores
1*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores
1*
Hardware threads per core
1*

System configuration

Detailed specifications

Specifications ยท 77 fields
ifu CPU microarchitecture
2*
metal layers Manufacturing process
4*
lsfu CPU microarchitecture
1*
fpfu CPU microarchitecture
3*
date
1996-01-01*
date
1996-01-01*
date
1996-01-01*
date
1996-01-01*
date
1996-01-01*
tfu CPU microarchitecture
6*
vdd nom Manufacturing process
3.3*
clock
250*
clock
195*
clock
180*
clock
200*
clock
196*
max inst decoded CPU microarchitecture
4*
rob size CPU microarchitecture
32*
hw nthreadspercore
1*
hw nthreadspercore
1*
hw nthreadspercore
1*
hw nthreadspercore
1*
hw nthreadspercore
1*
iwindow CPU microarchitecture
5*
hw ncores
1*
hw ncores
1*
hw ncores
1*
hw ncores
1*
hw ncores
1*
bht size CPU microarchitecture
512*
btb size CPU microarchitecture
512*
bus width
64*
bus width
64*
bus width
64*
bus width
64*
bus width
64*
arch int reg CPU microarchitecture
32*
transistors
6.8*
transistors
6.8*
transistors
6.8*
transistors
6.8*
transistors
6.8*
arch fp reg CPU microarchitecture
32*
die size
298*
die size
298*
die size
298*
die size
298*
die size
298*
total arch reg CPU microarchitecture
64*
vdd low
3.3*
vdd low
3.3*
vdd low
3.3*
vdd low
3.3*
vdd low
3.3*
vdd high
3.3*
vdd high
3.3*
vdd high
3.3*
vdd high
3.3*
vdd high
3.3*
out of order CPU microarchitecture
t*
memory bw CPU microarchitecture
3,200*
integrated mc CPU microarchitecture
f*
l1i CPU cache configuration
32*
name Processor code name
T5*
name Processor family
R10000*
name CPU microarchitecture
R10000*
l1d CPU cache configuration
32*
l2 shared CPU cache configuration
1,024*
l2 shared CPU cache configuration
4,096*
l2 shared CPU cache configuration
2,048*
year Manufacturing process
1995*
fp pipestages CPU microarchitecture
7*
technology Manufacturing process
CMOS*
feature size Manufacturing process
0.35*
int pipestages CPU microarchitecture
5*
channel length Manufacturing process
0.35*
max uop issued per cycle CPU microarchitecture
5*

* Provisional data