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CPU

AMD

AMD Athlon 64 1500+

Processor Released Nov 7, 2004

CPU cores: 1
CPU threads: 1^*
Thermal design power: 9 W

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1
CPU threads: 1^*
Base clock: 1 GHz
CPU reference clock: 200 MHz^*
Reported CPU clock: 1 GHz^*
L2 cache: 0.5 MB
Socket / package: 754
Process node: 90 nm^*
Reported chip die area: 84 mm²^*
Chip/package TDP: 9 W^*
Transistors: 69 million^*

Cache hierarchy

L2 / total
Level
L2
Scope
total
Size
0.5 MB

Compatible sockets

754

Power specifications

Thermal design power: 9 W

System configuration

Detailed specifications

Specifications 1 · 8 fields

Release: Nov 7th, 2005^*
Name: Athlon 64 1500+^*
Codename: Venice^*
Cores: 1^*
Clock: 1,000^* MHz
Socket: Socket 754^*
Process: 90^* nm
TDP: 9^* W

Specifications 2 · 27 fields

name: Athlon 64 1500+^*
Release Date: Nov 7th, 2005^*
Part#: ADC1500B2X4BX^*
Frequency: 1,000^* MHz
Base Clock: 200^* MHz
Multiplier: 5.0x^*
Multiplier Unlocked: No^*
Voltage: 0.9^* V
Codename: Venice^*
Socket: AMD Socket 754^*
Generation: Athlon 64 (Venice)^*
Memory Support: DDR1^*
ECC Memory: No^*
# of Cores: 1^*
# of Threads: 1^*
SMP # CPUs: 1^*
Integrated Graphics: On certain motherboards (Chipset feature)^*
Cache L1: 128^* KB
Cache L2: 512^* KB
Features: MMX, 3DNow!, SSE, SSE2, SSE3, AMD64^*
Memory Bus: Single-channel^*
Process Size: 90^* nm
Transistors: 69 million^*
Die Size: 84^* mm²
Package: µPGA^*
Market: Desktop^*
Production Status: End-of-life^*

Specifications 3 · 9 fields

Vendor: AMD^*
Product: AMD Athlon 64 1500+^*
Type: CPU^*
Release Date: 2005-11-07^*
Process Size (nm): 90^* nm
TDP (W): 9^* W
Die Size (mm^2): 84^* mm²
Transistors (million): 69^*
Freq (MHz): 1,000^* MHz

Specifications 4 · 1 fields

cores

1 cores

Scope and conditions

scope: Exact existing CPU source identity and brand. Core count per listed processor, not per installed system. Full ancestor section path and table subgroup retained. No core count from product-name tokens, cache multipliers, socket count or family/codename knowledge. No thread/SMT count inferred. Existing observations, variants, dates, units and benchmarks unchanged.

* Provisional data