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CONFRONTA.

CPU

AMD

AMD Athlon 64 1500+

Processore Uscita Nov 7, 2004

Core CPU: 1
Thread CPU: 1^*
Potenza termica di progetto: 9 W

Non sono ancora disponibili benchmark associati a questa scheda.

Elaborazione e piattaforma

Core CPU: 1
Thread CPU: 1^*
Frequenza base: 1 GHz
Clock di riferimento CPU: 200 MHz^*
Frequenza CPU riportata: 1 GHz^*
Cache L2: 0,5 MB
Socket / package: 754
Nodo produttivo: 90 nm^*
Area del chip dichiarata: 84 mm²^*
TDP chip/package: 9 W^*
Transistor: 69 million^*

Gerarchia cache

L2 / total
Livello
L2
Ambito
total
Dimensione
0,5 MB

Socket compatibili

754

Specifiche di potenza

Potenza termica di progetto: 9 W

Configurazione di sistema

Specifiche dettagliate

Specifiche 1 · 8 campi

Release: Nov 7th, 2005^*
Name: Athlon 64 1500+^*
Codename: Venice^*
Cores: 1^*
Clock: 1.000^* MHz
Socket: Socket 754^*
Process: 90^* nm
TDP: 9^* W

Specifiche 2 · 27 campi

name: Athlon 64 1500+^*
Release Date: Nov 7th, 2005^*
Part#: ADC1500B2X4BX^*
Frequency: 1.000^* MHz
Base Clock: 200^* MHz
Multiplier: 5.0x^*
Multiplier Unlocked: No^*
Voltage: 0,9^* V
Codename: Venice^*
Socket: AMD Socket 754^*
Generation: Athlon 64 (Venice)^*
Memory Support: DDR1^*
ECC Memory: No^*
# of Cores: 1^*
# of Threads: 1^*
SMP # CPUs: 1^*
Integrated Graphics: On certain motherboards (Chipset feature)^*
Cache L1: 128^* KB
Cache L2: 512^* KB
Features: MMX, 3DNow!, SSE, SSE2, SSE3, AMD64^*
Memory Bus: Single-channel^*
Process Size: 90^* nm
Transistors: 69 million^*
Die Size: 84^* mm²
Package: µPGA^*
Market: Desktop^*
Production Status: End-of-life^*

Specifiche 3 · 9 campi

Vendor: AMD^*
Product: AMD Athlon 64 1500+^*
Type: CPU^*
Release Date: 2005-11-07^*
Process Size (nm): 90^* nm
TDP (W): 9^* W
Die Size (mm^2): 84^* mm²
Transistors (million): 69^*
Freq (MHz): 1.000^* MHz

Specifiche 4 · 1 campi

cores

1 cores

Ambito e condizioni

scope: Exact existing CPU source identity and brand. Core count per listed processor, not per installed system. Full ancestor section path and table subgroup retained. No core count from product-name tokens, cache multipliers, socket count or family/codename knowledge. No thread/SMT count inferred. Existing observations, variants, dates, units and benchmarks unchanged.

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