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AcceleratorsBiren BR104
Accelerators
- Process node
- 7 nm*
Processing & platform
- Architecture
- Biren*
- Process node
- 7 nm*
- Chip foundry
- TSMC*
- Compute processor
- BR104*
- Device memory type
- HBM2e*
- Host interface
- PCIe 5.0 x16*
- Declared accelerator TDP
- 300 W*
Memory & storage
- Memory bus
- 2,048 bit*
- Rated memory bandwidth
- 819 GB/s*
System configuration
Detailed specifications
Specifications ยท 15 fields
- Architecture
- Biren*
- Reported theoretical BF16 peak
- 512.0* TFLOPS
Scope and conditions
- Arithmetic density
- Not stated*
- Host interface
- PCIe 5.0 x16*
- Memory bus
- 2,048* bit
- Reported theoretical FP16 peak
- 512.0* TFLOPS
Scope and conditions
- Arithmetic density
- Not stated*
- Reported theoretical INT8 peak
- 1,024.0* TOPS
Scope and conditions
- Arithmetic density
- Not stated*
- Chip foundry
- TSMC*
- Process node declaration
- 7 nm*
- Compute processor
- BR104*
- Declared device memory (unit not stated)
- 32*
- Rated memory bandwidth
- 819 GB/s*
- Device memory type
- HBM2e*
- 2:4 tensor sparsity
- No*
- Declared accelerator TDP
- 300 W*
- Reported theoretical TF32 peak
- 256.0* TFLOPS
Scope and conditions
- Arithmetic density
- Not stated*
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* Provisional data