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SoC

Zilog

Zilog Z8F0830PH020SG

System on a chip

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 33 fields

Architecture declaration

8^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Component type

MCU^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Clone designation

no^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Core design

eZ8^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Declared processor cores

1^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Family

eZ8^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Floating-point unit declaration

No^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Model designation: F0830^*
Package: Skinny PDIP-20^*

Maximum or typical clock declaration

20^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Model designation: F0830^*
Package: Skinny PDIP-20^*

Environmental designation

Yes^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Instruction set

eZ8^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Instruction-set architecture

Z8^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

L1 data cache declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

L1 instruction cache declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Unified L1 cache declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

L2 cache declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

L3 cache declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Power-saving features

STOP mode^*
HALT mode^*
Peripheral Level Power Control^*
Power Control Register Definitions^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Manufacturer

Zilog^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Military specification declaration

no^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Model designation

F0830^*

Scope and conditions

Package: Skinny PDIP-20^*

Multiprocessing declaration

No^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

On-chip peripherals

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Package

Skinny PDIP-20^*

Scope and conditions

Model designation: F0830^*

Part number

Z8F0830PH020SG^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Fabrication technology

CMOS^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

On-chip RAM declaration

256^* B

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

On-chip ROM declaration

8^* KiB

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

ROM type

flash^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Subfamily

Encore!^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Temperature grade

Commercial^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

Temperature range declaration

0^* – 70^* °C

Scope and conditions

Temperature reference: Unspecified^*
Model designation: F0830^*
Package: Skinny PDIP-20^*

Core supply voltage range

2.7^* – 3.6^* V

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

I/O supply voltage

3.3/5V^*

Scope and conditions

Model designation: F0830^*
Package: Skinny PDIP-20^*

* Provisional data