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Zilog

Zilog Z861212PE

System on a chip

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 34 fields

Component type

MCU^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Clone designation

no^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Technical notes

Development version of the Zilog Z6811^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Core design

Z8^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Declared processor cores

1^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Core designer

Zilog^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

External data bus declaration

8^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Family

Z8^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Floating-point unit declaration

No^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Model designation: Z8612^*
Package: PDIP-40^*

Maximum or typical clock declaration

12^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Model designation: Z8612^*
Package: PDIP-40^*

Instruction set

Z8^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

I/O logic compatibility

TTL^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Instruction-set architecture

Z8^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

L1 data cache declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

L1 instruction cache declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Unified L1 cache declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

L2 cache declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

L3 cache declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Manufacturer

Zilog^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Military specification declaration

no^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Model designation

Z8612^*

Scope and conditions

Package: PDIP-40^*

Multiprocessing declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

On-chip peripherals

Clock generator^*
counter/timers^*
interrupt controller^*
UART^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Package

PDIP-40^*

Scope and conditions

Model designation: Z8612^*

Part number

Z861212PE^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

On-chip RAM declaration

128^* B

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

On-chip ROM declaration

No^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Socket or package footprint

DIP-40^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Subfamily

Z8611/12/13^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Temperature grade

Industrial^*

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Temperature range declaration

-40^* – 85^* °C

Scope and conditions

Temperature reference: Unspecified^*
Model designation: Z8612^*
Package: PDIP-40^*

Core supply voltage range

4.75^* – 5.25^* V

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

Typical core supply voltage

5^* V

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

I/O supply voltage

5^* V

Scope and conditions

Model designation: Z8612^*
Package: PDIP-40^*

* Provisional data