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CPU
Zilog

Zilog Z8001ACS

Processor

CPU cores
1*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores
1*

System configuration

Detailed specifications

Specifications · 26 fields
Address bus declaration
16*
Scope and conditions
Package
CDIP-40*
Architecture declaration
16*
Scope and conditions
Package
CDIP-40*
Bus details
Shared Address/Data bus*
Scope and conditions
Package
CDIP-40*
Component type
CPU*
Scope and conditions
Package
CDIP-40*
Clone designation
no*
Scope and conditions
Package
CDIP-40*
Technical notes
Non-segmented CPU*
Scope and conditions
Package
CDIP-40*
Core design
Z8000*
Scope and conditions
Package
CDIP-40*
Declared processor cores
1*
Scope and conditions
Package
CDIP-40*
Core designer
Zilog*
Scope and conditions
Package
CDIP-40*
External data bus declaration
16*
Scope and conditions
Package
CDIP-40*
Family
Z8000*
Scope and conditions
Package
CDIP-40*
Maximum or typical clock declaration
6* MHz
Scope and conditions
Clock type
Maximum or typical; base or boost role unspecified*
Package
CDIP-40*
L1 data cache declaration
No*
Scope and conditions
Package
CDIP-40*
L1 instruction cache declaration
No*
Scope and conditions
Package
CDIP-40*
Unified L1 cache declaration
No*
Scope and conditions
Package
CDIP-40*
L2 cache declaration
No*
Scope and conditions
Package
CDIP-40*
L3 cache declaration
No*
Scope and conditions
Package
CDIP-40*
Manufacturer
Zilog*
Scope and conditions
Package
CDIP-40*
Package
CDIP-40*
Part number
Z8001ACS*
Scope and conditions
Package
CDIP-40*
Maximum RAM declaration
8* MiB
Scope and conditions
Package
CDIP-40*
Socket or package footprint
DIP-40*
Scope and conditions
Package
CDIP-40*
Subfamily
Z8001*
Scope and conditions
Package
CDIP-40*
Temperature grade
Commercial*
Scope and conditions
Package
CDIP-40*
Temperature range declaration
0* – 70* °C
Scope and conditions
Temperature reference
Unspecified*
Package
CDIP-40*
Virtual memory declaration
Using Z8004*
Scope and conditions
Unit
Unspecified*
Package
CDIP-40*

* Provisional data