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VIA Nano

Processor

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System configuration

Detailed specifications

Specifications 1 · 17 fields

Instruction set

IA-32, x86-64^*

Core design 1

Isaiah (CN)^*

Designer

Centaur Technology^*

Instruction extensions

MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1 (3000, X2, QuadCore), SSE4.2 (C), PadLock (AES, RNG, SHA)^*

Front-side bus variants: upper endpoint

1,066^* MHz

Front-side bus variants: lower endpoint

533^* MHz

L1 cache and allocation

64 KiB instruction + 64 KiB data per core^*

L2 cache and allocation

1 MiB per core, exclusive^*

Manufacturer 1

Fujitsu^*

Manufacturer 2

TSMC^*

Microarchitecture

VIA Isaiah^*

CPU core options

• 1^*
• 2^*
• 4^*

Package option 1

Ball grid array (soldered)^*

Predecessor

VIA C7^*

Manufacturing process option 1

40 nm^*

Manufacturing process option 2

65 nm^*

Marketed by

VIA Technologies^*

Specifications 2 · 1 fields

Instruction set

x86-64^*

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