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CPU

Transmeta

Transmeta TM5600-13

Processor

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*
Process node: 180 nm^*

System configuration

Detailed specifications

Specifications · 35 fields

Bus clock declaration

133^* MHz

Scope and conditions

Package: CBGA-474^*

Architecture declaration

32^*

Scope and conditions

Package: CBGA-474^*

Component type

CPU^*

Scope and conditions

Package: CBGA-474^*

Clock multiplier

4^*

Scope and conditions

Package: CBGA-474^*

Technical notes

Requires Transmeta's x86 Code Morphing software to run x86 code, Values for bus frequency and clock multiplier are provided for normal operation. If LongRun is enabled the bus frequency and clock multiplier may be adjusted to match processor speed.^*

Scope and conditions

Package: CBGA-474^*

Core design

TM5600^*

Scope and conditions

Package: CBGA-474^*

Declared processor cores

1^*

Scope and conditions

Package: CBGA-474^*

Core designer

Transmeta^*

Scope and conditions

Package: CBGA-474^*

External data bus declaration

64^*

Scope and conditions

Package: CBGA-474^*

Family

Crusoe^*

Scope and conditions

Package: CBGA-474^*

Floating-point unit declaration

Integrated^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: CBGA-474^*

Maximum or typical clock declaration

533^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: CBGA-474^*

L1 data cache declaration

64^* KiB

Scope and conditions

Package: CBGA-474^*

L1 data cache organization

16-way set associative^*

Scope and conditions

Package: CBGA-474^*

L1 instruction cache declaration

64^* KiB

Scope and conditions

Package: CBGA-474^*

L1 instruction cache organization

8-way set associative^*

Scope and conditions

Package: CBGA-474^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: CBGA-474^*

L2 cache declaration

512^* KiB

Scope and conditions

Package: CBGA-474^*

L2 cache organization

write-back 4-way set associative^*

Scope and conditions

Package: CBGA-474^*

Power-saving features

LongRun power management^*
Auto Halt^*
Quick Start^*
Deep Sleep^*

Scope and conditions

Package: CBGA-474^*

Manufacturer

Transmeta^*

Scope and conditions

Package: CBGA-474^*

On-chip peripherals

PCI 2.1 compliant PCI bus controller^*
64-bit SDR RAM memory controller^*
64-bit DDR RAM memory controller^*

Scope and conditions

Package: CBGA-474^*

Package

CBGA-474^*

Package dimensions

32.5 x 25 mm^2^*

Scope and conditions

Package: CBGA-474^*

Part number

TM5600-13^*

Scope and conditions

Package: CBGA-474^*

Pipeline declaration

7 stage integer pipeline, 10-stage FP pipeline^*

Scope and conditions

Package: CBGA-474^*

Maximum power declaration

8.25^* W

Scope and conditions

Package: CBGA-474^*

Minimum power declaration

0.1^* W

Scope and conditions

Condition: (Deep Sleep mode)^*
Package: CBGA-474^*

Typical power declaration

0.7^* W

Scope and conditions

Package: CBGA-474^*

Fabrication node declaration

0.18^* µm

Scope and conditions

Package: CBGA-474^*

Fabrication technology

CMOS^*

Scope and conditions

Package: CBGA-474^*

RAM type

DDR/SDR^*

Scope and conditions

Package: CBGA-474^*

Temperature range declaration

0^* – 85^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: CBGA-474^*

Core supply voltage range

1.2^* – 1.6^* V

Scope and conditions

Package: CBGA-474^*

I/O supply voltage

2.5/3.3V^*

Scope and conditions

Package: CBGA-474^*

* Provisional data