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CPU

TI TMX99105-24 (sample)

Processor

CPU cores: 1^*
Thermal design power: 1 W^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

Power specifications

Thermal design power: 1 W^*

System configuration

Detailed specifications

Specifications · 32 fields

Address bus declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Architecture declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Component type

CPU^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Clone designation

no^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Technical notes

Only samples of this part was released^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Core design

TMS99105^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Declared processor cores

1^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Core designer

TI^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

External data bus declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Family

TMS99000^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

External clock declaration

24^* MHz

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Maximum or typical clock declaration

6^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Instruction-set architecture

TMS9900^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

L1 data cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

L2 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

L3 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Manufacturer

TI^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

On-chip peripherals

Clock generator^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Package

Side-brazed CDIP-40^*

Scope and conditions

Production designation: Sample^*

Part number

TMX99105-24 (sample)^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Thermal design power declaration

1^* W

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Fabrication technology

N-channel silicon-gate SMOS technology^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Production designation

Sample^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip RAM declaration

32^* B

Scope and conditions

Condition: Macrostore memory^*
Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Maximum RAM declaration

64^* KiB

Scope and conditions

Condition: data, 64KiB instruction^*
Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Socket or package footprint

DIP-40^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Temperature grade

Commercial^*

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Temperature range declaration

0^* – 70^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: Side-brazed CDIP-40^*
Production designation: Sample^*

Typical core supply voltage

5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

I/O supply voltage

5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*
Production designation: Sample^*

* Provisional data