Sun UltraSPARC

Processor

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*
Hardware threads per core: 1^*

System configuration

Detailed specifications

Specifications · 74 fields

ifu CPU microarchitecture: 2^*
metal layers Manufacturing process: 4^*
lsfu CPU microarchitecture: 1^*
fpfu CPU microarchitecture: 5^*
date: 1995-11-01^*
date: 1995-11-01^*
date: 1995-11-01^*
date: 1995-11-01^*
date: 1995-11-01^*
tfu CPU microarchitecture: 9^*
clock: 167^*
clock: 248^*
clock: 200^*
clock: 296^*
clock: 143^*
max inst decoded CPU microarchitecture: 4^*
hw nthreadspercore: 1^*
hw nthreadspercore: 1^*
hw nthreadspercore: 1^*
hw nthreadspercore: 1^*
hw nthreadspercore: 1^*
iwindow CPU microarchitecture: 4^*
hw ncores: 1^*
hw ncores: 1^*
hw ncores: 1^*
hw ncores: 1^*
hw ncores: 1^*
if queue CPU microarchitecture: 12^*
bht size CPU microarchitecture: 2,048^*
btb size CPU microarchitecture: 1,024^*
bus width: 64^*
bus width: 64^*
bus width: 64^*
bus width: 64^*
bus width: 64^*
arch int reg CPU microarchitecture: 32^*
transistors: 5.2^*
transistors: 5.2^*
transistors: 5.2^*
transistors: 5.2^*
transistors: 5.2^*
arch fp reg CPU microarchitecture: 32^*
die size: 315^*
die size: 315^*
die size: 315^*
die size: 315^*
die size: 315^*
vdd low: 3.3^*
vdd low: 3.3^*
vdd low: 3.3^*
vdd low: 3.3^*
vdd low: 3.3^*
vdd high: 3.3^*
vdd high: 3.3^*
vdd high: 3.3^*
vdd high: 3.3^*
vdd high: 3.3^*
out of order CPU microarchitecture: f^*
l1i CPU cache configuration: 16^*
name Processor family: UltraSPARC^*
name Processor code name: Spitfire^*
name CPU microarchitecture: UltraSPARC^*
l1d CPU cache configuration: 16^*
l2 shared CPU cache configuration: 1,024^*
l2 shared CPU cache configuration: 2,048^*
l2 shared CPU cache configuration: 512^*
name Manufacturing process: EPIC-3^*
year Manufacturing process: 1995^*
fp pipestages CPU microarchitecture: 9^*
technology Manufacturing process: CMOS^*
feature size Manufacturing process: 0.5^*
int pipestages CPU microarchitecture: 9^*
channel length Manufacturing process: 0.5^*
max uop issued per cycle CPU microarchitecture: 4^*

* Provisional data

Processing & platform

System configuration

Detailed specifications

Devices using this component