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Component references

Signetics

Signetics N8X305N

Component references

System configuration

Detailed specifications

Specifications · 19 fields

Bus details

13-bit instruction address bus, 16-bit instruction bus, 8-bit multiplexed I/O data/address bus^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Core design

8X305^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Declared processor cores

1^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Core designer

Signetics^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Family

8X300^*

Scope and conditions

Package: (0.9in) PDIP-50^*

I/O logic compatibility

TTL^*

Scope and conditions

Package: (0.9in) PDIP-50^*

L1 data cache declaration

No^*

Scope and conditions

Package: (0.9in) PDIP-50^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: (0.9in) PDIP-50^*

L2 cache declaration

No^*

Scope and conditions

Package: (0.9in) PDIP-50^*

L3 cache declaration

No^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Manufacturer

Signetics^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Package

(0.9in) PDIP-50^*

Part number

N8X305N^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Fabrication technology

Bipolar Schottky^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Socket or package footprint

(0.9in) DIP-50^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Subfamily

8X305^*

Scope and conditions

Package: (0.9in) PDIP-50^*

Typical core supply voltage

5^* V

Scope and conditions

Package: (0.9in) PDIP-50^*

I/O supply voltage

5^* V

Scope and conditions

Package: (0.9in) PDIP-50^*

* Provisional data