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CPU

Not reported

RISC Single Chip

Processor

No matched benchmark results are available for this entry yet.

System configuration

Detailed specifications

Specifications · 5 fields

Unified cache

Capacity: 8^* KB
Associativity: 2^*
Cache line: 64^* bytes
Policy: Store-through; LRU replacement^*

Clocks and execution units

Clock options: 33^* MHz
45^* MHz
Execution units: Fixed point^*
Floating point^*
Branch processor^*
Integer pipeline stages: 3^*
Floating-point pipeline stages: 4^*
Floating-point multiply-add array width: 32^* bit

Processor design

Designer and manufacturer: IBM^*
Instruction set: POWER^*
Design lineage: Feature-reduced single-chip POWER1 implementation^*
Example systems: RS/6000 Model 220^*
RS/6000 Model 230^*

Memory interface and ECC

Bus width: 72^* bit
Data path: 64^* bit
ECC bits: 8^*
ECC capability: Single-bit correction^*
Memory modules: Industry-standard SIMMs^*

Silicon and package

Approximate transistors: 1^* million
Die width: 14.9^* mm
Die height: 15.2^* mm
Die area: 226.48^* mm²
Minimum process feature: 0.8^* µm
Technology: CMOS^*
Wiring levels: 3^*
Package: Ceramic PGA^*
Package width: 36^* mm
Package height: 36^* mm
Signal pins: 201^*
Supply voltage: 3.6^* V
Power at 33 MHz: 4^* W

* Provisional data