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SoC

RCA

RCA CDP1804D

System on a chip

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 34 fields

Address bus declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Architecture declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Bus bandwidth declaration

2MIB/s @ 5V / 4MiB/s @ 10V^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Component type

MCU^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Clone designation

no^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core design

1804^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Declared processor cores

1^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core designer

RCA^*

Scope and conditions

Package: Side-brazed CDIP-40^*

External data bus declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Family

1804^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Floating-point unit declaration

No^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: Side-brazed CDIP-40^*

Maximum or typical clock declaration

4^* MHz

Scope and conditions

Condition: @ 5V / 8MHz @ 10V^*
Clock type: Maximum or typical; base or boost role unspecified^*
Package: Side-brazed CDIP-40^*

Minimum clock declaration

DC^*

Scope and conditions

Unit: Unspecified^*
Package: Side-brazed CDIP-40^*

Instruction set

1804^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Instruction-set architecture

1802^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 data cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L2 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L3 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Power-saving features

IDLE mode^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Manufacturer

RCA^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip peripherals

8-bit counter/timer^*
clock generator^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Package

Side-brazed CDIP-40^*

Part number

CDP1804D^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Typical power declaration

8^* mW

Scope and conditions

Condition: @ 5V; 80mW @ 10V^*
Package: Side-brazed CDIP-40^*

Fabrication technology

CMOS^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip RAM declaration

64^* B

Scope and conditions

Package: Side-brazed CDIP-40^*

Maximum RAM declaration

64^* KiB

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip ROM declaration

2^* KiB

Scope and conditions

Package: Side-brazed CDIP-40^*

Socket or package footprint

DIP-40^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature grade

Military^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature range declaration

-55^* – 125^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: Side-brazed CDIP-40^*

Core supply voltage range

4^* – 10.5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

* Provisional data