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QorIQ

Processor

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System configuration

Detailed specifications

Specifications · 32 fields

Communications-processor family

Designer: NXP Semiconductors / Freescale^*
Instruction families: ARM^*
Power ISA^*
Brand announced: 2008-06^*
Families: P series^*
T series^*
Layerscape LS^*
Layerscape LX^*

Layerscape LA1575 configuration

Model

LA1575^*

CPU cores

2^*

CPU core

ARM Cortex-A53^*

Clock

1.4^* GHz

PCI Express interfaces

Count: 1^*
Generation: 3.0^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

Layerscape LS1012A configuration

Model

LS1012A^*

CPU cores

1^*

CPU core

ARM Cortex-A53^*

Clock

1.0^* GHz

PCI Express interfaces

Count: 1^*
Generation: 2.0^*

SerDes lanes

3^*

SATA

Yes^*

Integrated SEC engine

Yes^*

Layerscape LS1020A configuration

Model

LS1020A^*

CPU cores

2^*

CPU core

ARM Cortex-A7^*

Clock

1.2^* GHz

PCI Express interfaces

Count: 2^*
Generation: 2.0^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

QUICC engine

Yes^*

Layerscape LS1021A configuration

Model

LS1021A^*

CPU cores

2^*

CPU core

ARM Cortex-A7^*

Clock

1.2^* GHz

PCI Express interfaces

Count: 2^*
Generation: 2.0^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

QUICC engine

Yes^*

Layerscape LS1022A configuration

Model

LS1022A^*

CPU cores

2^*

CPU core

ARM Cortex-A7^*

Clock

0.6^* GHz

PCI Express interfaces

Count: 1^*
Generation: 2.0^*

SerDes lanes

1^*

SATA

No^*

Integrated SEC engine

Yes^*

Layerscape LS1024A configuration

Model

LS1024A^*

CPU cores

2^*

CPU core

ARM Cortex-A9^*

Clock

1.2^* GHz

PCI Express interfaces

Count: 2^*
Generation: 2.0^*

SerDes lanes

3^*

SATA

Yes^*

Integrated SEC engine

Yes^*

DCE/PME

Yes^*

Layerscape LS1028A configuration

Model

LS1028A^*

CPU cores

2^*

CPU core

ARM Cortex-A72^*

Clock

1.3^* GHz

PCI Express interfaces

Count: 2^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

Layerscape LS1043A configuration

Model

LS1043A^*

CPU cores

4^*

CPU core

ARM Cortex-A53^*

Clock

1.6^* GHz

PCI Express interfaces

Count: 3^*
Generation: 2.0^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

QUICC engine

Yes^*

Layerscape LS1046A configuration

Model

LS1046A^*

CPU cores

4^*

CPU core

ARM Cortex-A72^*

Clock

1.8^* GHz

PCI Express interfaces

Count: 3^*
Generation: 3.0^*

SerDes lanes

8^*

SATA

Yes^*

Integrated SEC engine

Yes^*

Layerscape LS1088A configuration

Model

LS1088A^*

CPU cores

8^*

CPU core

ARM Cortex-A53^*

Clock

1.6^* GHz

PCI Express interfaces

Count: 3^*
Generation: 3.0^*

SerDes lanes

4^*

SATA

Yes^*

Integrated SEC engine

Yes^*

QUICC engine

Yes^*

Layerscape LX2160A configuration

Model

LX2160A^*

CPU cores

16^*

CPU core

ARM Cortex-A72^*

Clock

2.2^* GHz

PCI Express interfaces

Count: 6^*

SerDes lanes

24^*

SATA

Yes^*

Integrated SEC engine

Yes^*

Layerscape LX2162A configuration

Model

LX2162A^*

CPU cores

16^*

CPU core

ARM Cortex-A72^*

Clock

2.0^* GHz

PCI Express interfaces

Count: 12^*
Generation: 3.0^*

SerDes lanes

12^*

SATA

Yes^*

Integrated SEC engine

Yes^*

P1 platform options

Clock range: 400^* – 800^* MHz
Memory types: DDR2^*
DDR3^*
Memory-controller width: 32^* bit
ECC: Yes^*
USB 2.0 controllers: 2^*
Package pins: 689^*
Package compatibility: P2 family pin layout^*

Named P1 configurations

Model
P1010^*
Cores
1^*
Core
e500^*
Clock
800^* MHz
L2
256^* kB
SerDes lanes
4^*
Gigabit Ethernet controllers
3^*
Model
P1011^*
Cores
1^*
Core
e500^*
Clock
800^* MHz
L2
256^* kB
SerDes lanes
4^*
Gigabit Ethernet controllers
3^*
Model
P1020^*
Cores
2^*
Core
e500^*
Clock
800^* MHz
Shared L2
256^* kB
SerDes lanes
4^*
Gigabit Ethernet controllers
3^*

P2 platform options

Clock endpoints

Minimum: 800^* MHz
Maximum: 1.2^* GHz

L2 cache

512^* kB

Gigabit Ethernet controllers

3^*

USB 2.0 controllers

1^*

Memory-controller width

64^* bit

Memory types

DDR2^*
DDR3^*

ECC

Yes^*

Package pins

689^*

Package compatibility

P1 family pin layout^*

Implementations

Model
P2010^*
Cores
1^*
Clock
1.2^* GHz
Model
P2020^*
Cores
2^*
Clock
1.2^* GHz
L2 allocation
Shared^*

P3041 configuration

Cores: 4^*
Core: e500mc^*
Clock: 1.5^* GHz
Per-core L2: 128^* kB
DDR3 controllers: 1^*
Memory-controller width: 64^* bit
Memory-controller rating: 1.3^* GHz
Process: 45^* nm
Power envelope: 12^* W

P4080 configuration

Cores: 8^*
Core: e500mc^*
Clock: 1.5^* GHz
Per-core L1 instruction: 32^* kB
Per-core L1 data: 32^* kB
Per-core L2: 128^* kB
L3 banks: 2^*
L3 per bank: 1^* MB
Memory controllers: 2^*
Memory-controller width: 64^* bit
Memory types: DDR2^*
DDR3^*
Maximum Gigabit Ethernet controllers: 8^*
Maximum 10-Gigabit Ethernet controllers: 2^*
PCI Express ports: 3^*
RapidIO interfaces: 2^*
USB 2 controllers: 2^*
Design power: Below 30 W^*
Process: 45^* nm
Technology: SOI^*
Sampling: 2009-08^*

P5 processor configurations

Model
P5010^*
Core
e5500^*
Cores
1^*
Clock
2.2^* GHz
L3
1^* MB
Process
45^* nm
Power envelope
30^* W
Model
P5020^*
Core
e5500^*
Cores
2^*
Clock
2.2^* GHz
L3 banks
2^*
L3 per bank
1^* MB
Process
45^* nm
Power envelope
30^* W
Model
P5021^*
Core
e5500^*
Cores
2^*
Clock
2.4^* GHz
DDR3/DDR3L rating
1.6^* GHz
Model
P5040^*
Core
e5500^*
Cores
4^*
Clock
2.4^* GHz
DDR3/DDR3L rating
1.6^* GHz

LS1028A CPU configuration

Model: LS1028A^*
Cores: 2^*
Core: Arm Cortex-A72^*
Word-size modes: 32^*
64^*
Maximum clock: 1.5^* GHz
Threads per core: 1^*
Per-core L1 instruction: 48^* KB
Per-core L1 data: 32^* KB
Shared L2: 1^* MB

LS1028A integrated graphics capabilities

Model: LS1028A^*
LCD controllers: 1^*
Display interfaces: DisplayPort^*
eDP^*
GPU geometry-rate claim: 100^* million triangles/s
GPU pixel-rate claim: 650^* million pixels/s
Theoretical FP32 peak: 10.4^* GFLOPS
Scope: Vendor hardware ceilings; not application benchmarks or measured frame rates^*

LS1028A memory and DMA

Model: LS1028A^*
Memory data width: 32^* bit
Memory types: DDR3L^*
DDR4^*
ECC: Yes^*
Maximum memory data rate: 1.6^* GT/s
qDMA controllers: 1^*
eDMA controllers: 1^*

LS1028A networking and PCI Express

Model

LS1028A^*

SerDes lanes

4^*

PCI Express controllers

2^*

PCI Express generation

3.0^*

PCI Express modes

Root Complex^*
Endpoint^*

TSN switch external ports

4^*

Switched Ethernet port rates

Ports: 4^*
Options: 1^* Gbit/s
2.5^* Gbit/s

Other Ethernet ports

Count
1^*
Rate options
- 1^* Gbit/s
- 2.5^* Gbit/s
Count
1^*
Rate
1^* Gbit/s

SATA controllers

1^*

SATA rate

6^* Gbit/s

LS1028A package and monitoring

Model: LS1028A^*
Thermal monitor: Yes^*
Package: FC-PBGA^*
Package width: 17^* mm
Package height: 17^* mm

LS1028A peripheral controllers

Model: LS1028A^*
USB controllers: 2^*
USB versions: 2.0^*
3.0^*
USB PHY: Integrated^*
eSDHC controllers: 2^*
SD version: 3.0^*
eMMC versions: 4.4^*
4.5^*
5.1^*
CAN controllers: 2^*
Optional CAN Flexible Data-rate: Yes^*
SPI controllers: 3^*
FlexSPI controllers: 1^*
I2C controllers: 8^*
16550 DUART controllers: 1^*
Low-power UARTs: 6^*
SAI interfaces: 6^*
GPIO: Yes^*

LX2080A platform configuration

Model: LX2080A^*
Cores: 8^*
L2 cache: 8^* MB
SerDes lanes: 24^*
Maximum PCI Express controllers: 6^*
PCI Express generation: 3^*
Memory controllers: 2^*
Memory type: DDR4^*
Maximum memory data rate: 3,200^* MT/s
Memory capacity ceiling: 256^* GB
Platform cache and packet buffer: 10^* MB
Maximum security accelerator claim: 50^* Gbit/s
Maximum compression/decompression claim: 100^* Gbit/s
Package width: 40^* mm
Package height: 40^* mm
Package pins: 1,517^*
Scope: Family comparison table; workload, memory population and shared I/O constraints apply^*

LX2120A platform configuration

Model: LX2120A^*
Cores: 12^*
L2 cache: 6^* MB
SerDes lanes: 24^*
Maximum PCI Express controllers: 6^*
PCI Express generation: 3^*
Memory controllers: 2^*
Memory type: DDR4^*
Maximum memory data rate: 3,200^* MT/s
Memory capacity ceiling: 256^* GB
Platform cache and packet buffer: 10^* MB
Maximum security accelerator claim: 50^* Gbit/s
Maximum compression/decompression claim: 100^* Gbit/s
Package width: 40^* mm
Package height: 40^* mm
Package pins: 1,517^*
Scope: Family comparison table; workload, memory population and shared I/O constraints apply^*

LX2160A platform configuration

Model: LX2160A^*
Cores: 16^*
L2 cache: 8^* MB
SerDes lanes: 24^*
Maximum PCI Express controllers: 6^*
PCI Express generation: 3^*
Memory controllers: 2^*
Memory type: DDR4^*
Maximum memory data rate: 3,200^* MT/s
Memory capacity ceiling: 256^* GB
Platform cache and packet buffer: 10^* MB
Maximum security accelerator claim: 50^* Gbit/s
Maximum compression/decompression claim: 100^* Gbit/s
Package width: 40^* mm
Package height: 40^* mm
Package pins: 1,517^*
Scope: Family comparison table; workload, memory population and shared I/O constraints apply^*

LX2160A processing and I/O limits

Model: LX2160A^*
Cores: 16^*
Core: Arm Cortex-A72^*
Maximum clock: 2.2^* GHz
Cache and on-chip memory: 18^* MB
SerDes lanes: 24^*
Maximum Ethernet ports: 16^*
Ethernet rate options: 1^* Gbit/s
2.5^* Gbit/s
10^* Gbit/s
25^* Gbit/s
40^* Gbit/s
50^* Gbit/s
100^* Gbit/s
Maximum L2 switching claim: 114^* Gbit/s
Maximum PCI Express lanes: 24^*
PCI Express generation: 3^*
Maximum PCI Express port width: 8^*
Security acceleration claim: 50^* Gbit/s
Compression/decompression engine claim: 100^* Gbit/s
Scope: Vendor ceilings; interface sharing and configuration apply; not benchmark runs^*

T1 processor configurations

Core

e5500^*

Core width

64^* bit

Clock range

1.2^* – 1.5^* GHz

L2 per core

256^* kB

Shared L3

256^* kB

Models

Model
T1013^*
Cores
1^*
SerDes lanes
4^*
Gigabit Ethernet ports
4^*
Ethernet switch
No^*
Model
T1014^*
Cores
1^*
SerDes lanes
4^*
Gigabit Ethernet ports
4^*
Ethernet switch
No^*
Model
T1020^*
Cores
2^*
Gigabit Ethernet ports
4^*
Switch ports
8^*
Model
T1022^*
Cores
2^*
Gigabit Ethernet ports
5^*
Ethernet switch
No^*
Model
T1023^*
Cores
2^*
SerDes lanes
4^*
Gigabit Ethernet ports
4^*
Ethernet switch
No^*
Model
T1024^*
Cores
2^*
SerDes lanes
4^*
Gigabit Ethernet ports
4^*
Ethernet switch
No^*
Model
T1040^*
Cores
4^*
SerDes lanes
8^*
Gigabit Ethernet ports
5^*
Switch ports
8^*
Model
T1042^*
Cores
4^*
SerDes lanes
8^*
Gigabit Ethernet ports
5^*
Ethernet switch
No^*

T2 processor configurations

Models: T2080^*
T2081^*
Core: e6500^*
Cores: 4^*
Threads per core: 2^*
Clock range: 1.5^* – 1.8^* GHz
T2081 pin-compatible families: T104x^*
T102x^*
Compatibility scope: Pin layout; not a board/software guarantee^*

T4 processor configurations

Model
T4240^*
Core
e6500^*
Core width
64^* bit
Threads per core
2^*
Cores
12^*
Memory controllers
3^*
Model
T4160^*
Core
e6500^*
Threads per core
2^*
Cores
8^*
Memory controllers
2^*
Model
T4080^*
Core
e6500^*
Threads per core
2^*
Cores
4^*
Memory controllers
2^*

* Provisional data