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PicoBlaze

Processor

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System configuration

Detailed specifications

Specifications · 4 fields

Soft-core architecture

Designer

Xilinx^*

Product type

FPGA/CPLD soft processor^*

Architecture

8-bit RISC^*

I/O address port

8^* bit

I/O data port

8^* bit

Use restriction

Xilinx devices^*

Documented implementation resources

FPGA slices

96^*

Scratchpad memory

64^* bytes

Call stack entries

31^*

Scope

Representative documented core; FPGA and core revision matter^*

Architectural instruction timing

Instruction duration

2^* clock cycles

Maximum interrupt response

5^* clock cycles

Instruction PROM

Words

1,024^*

Word width

18^* bit

Cores sharing a dual-port instruction PROM

2^*

Virtex-4 instruction-rate claim

Maximum instruction rate

100^* MIPS

Target

Virtex-4^*

Measurement status

Architectural/vendor claim; not a benchmark run^*

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