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CPU

NEC

NEC D30401RJ-50

Processor

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 32 fields

Alternative designation 1

VR4000SC-50^*

Scope and conditions

Package: Ceramic SPGA-447^*

Alternative designation 2

uPD30401RJ-50^*

Scope and conditions

Package: Ceramic SPGA-447^*

Alternative designation 3

μPD30401RJ-50^*

Scope and conditions

Package: Ceramic SPGA-447^*

Architecture declaration

64^*

Scope and conditions

Package: Ceramic SPGA-447^*

Component type

CPU^*

Scope and conditions

Package: Ceramic SPGA-447^*

Clock multiplier

2, 3 or 4^*

Scope and conditions

Package: Ceramic SPGA-447^*

Clone designation

no^*

Scope and conditions

Package: Ceramic SPGA-447^*

Technical notes

Internal pipeline operates at 100 MHz.^*

Scope and conditions

Package: Ceramic SPGA-447^*

Declared processor cores

1^*

Scope and conditions

Package: Ceramic SPGA-447^*

Family

R4000^*

Scope and conditions

Package: Ceramic SPGA-447^*

Floating-point unit declaration

integrated^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: Ceramic SPGA-447^*

Maximum or typical clock declaration

50^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: Ceramic SPGA-447^*

Instruction set

R4000^*

Scope and conditions

Package: Ceramic SPGA-447^*

Instruction-set architecture

MIPS^*

Scope and conditions

Package: Ceramic SPGA-447^*

L1 data cache declaration

8^* KiB

Scope and conditions

Package: Ceramic SPGA-447^*

L1 data cache organization

direct-mapped, can be expanded to 32 KiB^*

Scope and conditions

Package: Ceramic SPGA-447^*

L1 instruction cache declaration

8^* KiB

Scope and conditions

Package: Ceramic SPGA-447^*

L1 instruction cache organization

direct-mapped, can be expanded to 32 KiB^*

Scope and conditions

Package: Ceramic SPGA-447^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Ceramic SPGA-447^*

L2 cache declaration

ext. 128KiB to 4MiB^*

Scope and conditions

Package: Ceramic SPGA-447^*

L2 cache organization

128-bit^*

Scope and conditions

Package: Ceramic SPGA-447^*

L3 cache declaration

No^*

Scope and conditions

Package: Ceramic SPGA-447^*

Manufacturer

NEC^*

Scope and conditions

Package: Ceramic SPGA-447^*

Military specification declaration

no^*

Scope and conditions

Package: Ceramic SPGA-447^*

On-chip peripherals

L2 cache controller^*
System control processor^*
MMU^*

Scope and conditions

Package: Ceramic SPGA-447^*

Package

Ceramic SPGA-447^*

Part number

D30401RJ-50^*

Scope and conditions

Package: Ceramic SPGA-447^*

Pipeline declaration

8-stage^*

Scope and conditions

Package: Ceramic SPGA-447^*

Fabrication technology

CMOS^*

Scope and conditions

Package: Ceramic SPGA-447^*

Maximum RAM declaration

64^* GiB

Scope and conditions

Package: Ceramic SPGA-447^*

Transistor count declaration

1,300,000^*

Scope and conditions

Package: Ceramic SPGA-447^*

Virtual memory declaration

2^* GiB

Scope and conditions

Condition: (32-bit mode); 1 TiB (64-bit mode)^*
Package: Ceramic SPGA-447^*

* Provisional data