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CPU

National Semiconductor

National Semiconductor NSC800D-4

Processor

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 36 fields

Address bus declaration

16^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Architecture declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Bus details

Data bus shared with the address bus 0-7^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Component type

CPU^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core design

NSC800^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Declared processor cores

1^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core designer

National Semiconductor^*

Scope and conditions

Package: Side-brazed CDIP-40^*

External data bus declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Family

NSC800^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Floating-point unit declaration

No^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: Side-brazed CDIP-40^*

Maximum or typical clock declaration

4^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: Side-brazed CDIP-40^*

Instruction set

Z80^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Instruction-set architecture

Z80^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 data cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L2 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L3 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Power-saving features

power-save mode^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Manufacturer

National Semiconductor^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Military specification declaration

no^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip peripherals

Clock generator^*
bus controller^*
interrupt controller^*
DRAM refresh circuitry^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Package

Side-brazed CDIP-40^*

Part number

NSC800D-4^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Maximum power declaration

120^* mW

Scope and conditions

Package: Side-brazed CDIP-40^*

Typical power declaration

75^* mW

Scope and conditions

Package: Side-brazed CDIP-40^*

Fabrication technology

CMOS^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Maximum RAM declaration

64^* KiB

Scope and conditions

Package: Side-brazed CDIP-40^*

RAM type

DRAM^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Socket or package footprint

DIP-40^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature grade

Commercial^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature range declaration

0^* – 70^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: Side-brazed CDIP-40^*

Transistor count declaration

11,000^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core supply voltage range

2.4^* – 6^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

Typical core supply voltage

5^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

I/O supply voltage

Vcc^*

Scope and conditions

Unit: Unspecified^*
Package: Side-brazed CDIP-40^*

* Provisional data