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Motorola

Motorola MC146805E2S

System on a chip

CPU cores: 1^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*

System configuration

Detailed specifications

Specifications · 27 fields

Address bus declaration

12^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Architecture declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Component type

MCU^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core design

6805^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Declared processor cores

1^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Core designer

Motorola^*

Scope and conditions

Package: Side-brazed CDIP-40^*

External data bus declaration

8^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Family

6805^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Floating-point unit declaration

No^*

Scope and conditions

FPU implementation: Integrated or external scope unspecified^*
Package: Side-brazed CDIP-40^*

Maximum or typical clock declaration

1^* MHz

Scope and conditions

Clock type: Maximum or typical; base or boost role unspecified^*
Package: Side-brazed CDIP-40^*

L1 data cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L1 instruction cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Unified L1 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L2 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

L3 cache declaration

No^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Power-saving features

STOP^*
WAIT modes^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Manufacturer

Motorola^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip peripherals

Clock generator^*
timer/counter^*
interrupt controller^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Package

Side-brazed CDIP-40^*

Part number

MC146805E2S^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Minimum power declaration

25^* µW

Scope and conditions

Condition: (STOP mode)^*
Package: Side-brazed CDIP-40^*

Fabrication technology

CMOS^*

Scope and conditions

Package: Side-brazed CDIP-40^*

On-chip RAM declaration

112^* B

Scope and conditions

Package: Side-brazed CDIP-40^*

Maximum RAM declaration

8^* KiB

Scope and conditions

Package: Side-brazed CDIP-40^*

Socket or package footprint

DIP-40^*

Scope and conditions

Package: Side-brazed CDIP-40^*

Temperature range declaration

0^* – 70^* °C

Scope and conditions

Temperature reference: Unspecified^*
Package: Side-brazed CDIP-40^*

Core supply voltage range

3^* – 6^* V

Scope and conditions

Package: Side-brazed CDIP-40^*

* Provisional data