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CPU

Intel

Intel Timna

Processor

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System configuration

Detailed specifications

Specifications 1 · 4 fields

Design and status

Designer: Intel^*
Design site: Haifa, Israel^*
Announced: 1,999^*
Status: Cancelled^*
Cancellation date: 2000-09-29^*
Architecture lineage: P6-derived^*

Planned integrated graphics

Codename: Capitola^*
Design lineage: i752^*
i754^*

Planned memory interfaces

Initial memory type: RDRAM^*
Alternative: SDRAM through Memory Translator Hub^*

Proposed processor configuration

Clock options: 600^* – 700^* MHz
Front-side bus: 133^* MHz
L2 cache: 128^* KB
Process: 180^* nm

Specifications 2 · 3 fields

Manufacturer: Intel^*
Developer: Intel^*
Processor family or type: x86^*

* Provisional data