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CPUIntel Itanium 2
Processor
- CPU cores
- 1*
No matched benchmark results are available for this entry yet.
Processing & platform
- CPU cores
- 1*
- Hardware threads per core
- 1*
System configuration
Detailed specifications
Specifications ยท 49 fields
- ifu CPU microarchitecture
- 4*
- metal layers Manufacturing process
- 6*
- lsfu CPU microarchitecture
- 2*
- metal Manufacturing process
- aluminum*
- fpfu CPU microarchitecture
- 4*
- tfu CPU microarchitecture
- 17*
- clock
- 900*
- clock
- 1,660*
- max inst decoded CPU microarchitecture
- 6*
- hw nthreadspercore
- 1*
- hw nthreadspercore
- 1*
- iwindow CPU microarchitecture
- 6*
- hw ncores
- 1*
- hw ncores
- 1*
- if queue CPU microarchitecture
- 24*
- bht size CPU microarchitecture
- 20,000*
- tdp
- 122*
- btb size CPU microarchitecture
- 64*
- arch int reg CPU microarchitecture
- 1,064*
- transistors
- 592*
- arch fp reg CPU microarchitecture
- 128*
- die size
- 432*
- fanout Process gate-delay observation
- 1*
- fanout Process gate-delay observation
- 1*
- l1i CPU cache configuration
- 16*
- name Processor code name
- Mckinley*
- name Processor family
- Itanium 2*
- name Processor code name
- Madison*
- name CPU microarchitecture
- Mckinley*
- delay Process gate-delay observation
- 13*
- delay Process gate-delay observation
- 10.75*
- isa CPU microarchitecture
- IA-64*
- l1d CPU cache configuration
- 16*
- l2 shared CPU cache configuration
- 9,216*
- l2 shared CPU cache configuration
- 256*
- name Manufacturing process
- P858*
- vdd Process gate-delay observation
- 1.5*
- vdd Process gate-delay observation
- 1.3*
- gate type Process gate-delay observation
- inv*
- gate type Process gate-delay observation
- inv*
- l2 shared ncores CPU cache configuration
- 1*
- year Manufacturing process
- 1999*
- fp pipestages CPU microarchitecture
- 10*
- l3 shared CPU cache configuration
- 1,536*
- technology Manufacturing process
- CMOS*
- feature size Manufacturing process
- 0.18*
- int pipestages CPU microarchitecture
- 10*
- channel length Manufacturing process
- 0.13*
- max uop issued per cycle CPU microarchitecture
- 20*
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* Provisional data