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CPU
Intel

Intel Celeron M ULV 423

Processor

CPU cores
1
CPU threads
1*
Thermal design power
5.50 W

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores
1
CPU threads
1*
Base clock
1.07 GHz
L2 cache
1 MB
Socket / package
FCBGA6
Process node
65 nm*

Cache hierarchy

  • L2 / total
    Level
    L2
    Scope
    total
    Size
    1 MB
  • L2*
    Size
    1 MB*
    Level
    L2*
    Scope
    L2 Cache*

Compatible sockets

  • FCBGA6

Power specifications

Thermal design power
5.50 W

System configuration

Detailed specifications

Specifications 1 · 15 fields
cache size
1,024*
tdp
5.5*
socket
PBGA479*
cores
1*
vertical segment
Mobile*
status
Discontinued*
max temp
100*
package size
35mm x 35mm*
threads
1*
name
Intel Celeron M ULV 423*
processor number
423*
launch date
2006-02-01*
lithography
65*
bus speed
533*
base frequency
1,060*
Specifications 2 · 33 fields
Marketing Status
Discontinued*
Launch Date
Q1'06*
Embedded Options Available
Yes*
Servicing Status
End of Servicing Lifetime*
Sockets Supported
PBGA479*
Package Size
35mm x 35mm*
Processing Die Size
90 mm2*
# of Processing Die Transistors
151 million*
TJUNCTION
100* °C
Product Collection
Legacy Intel® Celeron® Processor*
Intel® Turbo Boost Technology ‡
No*
Intel® Hyper-Threading Technology ‡
No*
Intel® 64 ‡
No*
Instruction Set
32-bit*
Idle States
No*
Enhanced Intel SpeedStep® Technology
No*
Intel® Demand Based Switching
No*
Vertical Segment
Mobile*
Intel® Virtualization Technology (VT-x) ‡
No*
Processor Number
423*
Intel® Trusted Execution Technology ‡
No*
Execute Disable Bit ‡
Yes*
Lithography
65* nm
# of Cores
1*
Processor Base Frequency
1.06* GHz
Cache
1.0* MB
Scope and conditions
source_native_row_context
Cache description
L2 Cache*
Original declaration
1 MB L2 Cache*
Bus Speed
533* MHz
FSB Parity
No*
TDP
5.5* W
VID Voltage Range
0.85V-1.10V*
Scenario Design Power (SDP)
0* W
Physical Address Extensions
32-bit*
ECC Memory Supported ‡
No*
Specifications 3 · 7 fields
product
Celeron M ULV 423*
status
Discontinued*
releaseDate
2,006*
cores
1*
baseClock
1.06*
cache
1*
cacheInfo
L2 Cache*

* Provisional data