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CPU
Intel

Intel Celeron M ULV 373

Processor

CPU cores
1
CPU threads
1*
Thermal design power
5.50 W

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores
1
CPU threads
1*
Base clock
1 GHz
L2 cache
0.5 MB
Socket / package
H-PBGA479*
Process node
90 nm*

Cache hierarchy

  • L2 / total
    Level
    L2
    Scope
    total
    Size
    0.5 MB
  • L2*
    Size
    512 KB*
    Level
    L2*
    Scope
    L2 Cache*

Power specifications

Thermal design power
5.50 W

System configuration

Detailed specifications

Specifications 1 · 15 fields
cache size
512*
tdp
5.5*
socket
H-PBGA479*
cores
1*
vertical segment
Mobile*
status
Discontinued*
max temp
100*
package size
35mm x 35mm*
threads
1*
name
Intel Celeron M ULV 373*
processor number
373*
launch date
2004-05-01*
lithography
90*
bus speed
400*
base frequency
1,000*
Specifications 2 · 33 fields
Intel® Trusted Execution Technology ‡
No*
Execute Disable Bit ‡
Yes*
# of Cores
1*
Processor Base Frequency
1.0* GHz
Cache
512.0* KB
Scope and conditions
source_native_row_context
Cache description
L2 Cache*
Original declaration
512 KB L2 Cache*
Bus Speed
400* MHz
FSB Parity
No*
TDP
5.5* W
VID Voltage Range
0.876V-0.956V*
Scenario Design Power (SDP)
0* W
Marketing Status
Discontinued*
Launch Date
Q2'04*
Embedded Options Available
Yes*
Servicing Status
End of Servicing Lifetime*
ECC Memory Supported ‡
No*
Physical Address Extensions
32-bit*
Product Collection
Legacy Intel® Celeron® Processor*
Vertical Segment
Mobile*
Sockets Supported
H-PBGA479*
TJUNCTION
100* °C
Processor Number
373*
Package Size
35mm x 35mm*
Processing Die Size
87 mm2*
# of Processing Die Transistors
144 million*
Lithography
90* nm
Intel® Hyper-Threading Technology ‡
No*
Instruction Set
32-bit*
Intel® Turbo Boost Technology ‡
No*
Intel® Virtualization Technology (VT-x) ‡
No*
Intel® 64 ‡
No*
Idle States
No*
Enhanced Intel SpeedStep® Technology
No*
Intel® Demand Based Switching
No*
Specifications 3 · 7 fields
product
Celeron M ULV 373*
status
Discontinued*
releaseDate
2,004*
cores
1*
baseClock
1*
cache
0.5*
cacheInfo
L2 Cache*

* Provisional data