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CPU
Unspecified

EPYC 9224

Processor

CPU threads
48*
Maximum boost clock
3.7 GHz*
Thermal design power
200 W*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU threads
48*
Base clock
2.5 GHz*
CPU reference clock
100 MHz*
Maximum boost clock
3.7 GHz*
L3 cache
64 MB*
Socket / package
Socket SP5*

Memory & storage

Rated memory bandwidth
460.80 GB/s*

Power specifications

Thermal design power
200 W*

System configuration

Detailed specifications

Specifications 1 · 9 fields
Release
Nov 10th, 2022*
Name
EPYC 9224*
Codename
Genoa*
Cores
24 / 48*
Clock
2.5 to 3.7 GHz*
Socket
Socket SP5*
Process
5* nm
L3 Cache
64MB*
TDP
200* W
Specifications 2 · 36 fields
name
EPYC 9224*
Release Date
Nov 10th, 2022*
Part#
100-100000939*
Frequency
2.5* GHz
Turbo Clock
up to 3.7 GHz*
I/O Process Size
6* nm
I/O Die Size
397* mm²
Base Clock
100* MHz
Multiplier
25.0x*
Multiplier Unlocked
No*
I/O Transistors
11,000 million*
Codename
Genoa*
Socket
AMD Socket SP5*
Generation
EPYC (Zen 4 (Genoa))*
Memory Support
DDR5*
ECC Memory
Yes*
# of Cores
24*
# of Threads
48*
SMP # CPUs
2*
Cache L1
64 KB (per core)*
Cache L2
1 MB (per core)*
Features
MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, SSE4.1, SSE4.2, AES, AVX, AVX2, AVX-512, VNNI, BMI1, BMI2, BFloat16, SHA, F16C, FMA3, AMD64, EVP, AMD-V, SMAP, SMEP, X2AVIC, AIBRS, 5-level NPT, SMT, Precision Boost 2, XFR 2*
Foundry
TSMC*
Rated Speed
4,800* MT/s
Memory Bus
Twelve-channel*
Memory Bandwidth
460.8* GB/s
Launch Price
$1,825*
PCI-Express
Gen 5, 128 Lanes (CPU only)*
Process Size
5* nm
Cache L3
64 MB (shared)*
Configurable TDP
200-240 W*
Transistors
26,280 million*
Die Size
4x 72 mm²*
Package
FC-LGA6096*
Market
Server/Workstation*
Production Status
Active*

* Provisional data