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CPU
Unspecified

EPYC 7352

Processor

CPU threads
48*
Maximum boost clock
3.2 GHz*
Thermal design power
155 W*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU threads
48*
Base clock
2.3 GHz*
CPU reference clock
100 MHz*
Maximum boost clock
3.2 GHz*
L3 cache
128 MB*
Socket / package
AMD Socket SP3*

Memory & storage

Rated memory bandwidth
204.80 GB/s*

Power specifications

Thermal design power
155 W*

System configuration

Detailed specifications

Specifications 1 · 9 fields
Release
Aug 7th, 2019*
Name
EPYC 7352*
Codename
Rome*
Cores
24 / 48*
Clock
2.4 to 3.3 GHz*
Socket
Socket SP3*
Process
7* nm
L3 Cache
128MB*
TDP
155* W
Specifications 2 · 40 fields
name
EPYC 7352*
Release Date
Aug 7th, 2019*
Part#
100-000000077*
Frequency
2.3* GHz
Turbo Clock
up to 3.2 GHz*
I/O Process Size
14* nm
I/O Die Size
416* mm²
Base Clock
100* MHz
Multiplier
23.0x*
Multiplier Unlocked
No*
I/O Transistors
9,100 million*
# of CCDs
4*
Cores per CCD
6*
Total L3
128* MB
Per-Socket PCI-Express
Gen 4, 64 Lanes*
Codename
Rome*
Socket
AMD Socket SP3*
Generation
EPYC (Zen 2 (Rome))*
Memory Support
DDR4*
ECC Memory
Yes*
# of Cores
24*
# of Threads
48*
SMP # CPUs
2*
Cache L1
96 KB (per core)*
Cache L2
512 KB (per core)*
Features
MMX, EMMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4A, AVX, AVX2, ABM, BMI1, BMI2, FMA3, AES, RdRand, SHA, ADX, CLMUL, F16C, Real, Protected, SMM, FPU, NX bit, SMT, AMD-Vi, AMD-V, SME, TSME, SEV, x2APIC, SenseMi, Boost 2*
Foundry
TSMC*
Rated Speed
3,200* MT/s
Memory Bus
Eight-channel*
Memory Bandwidth
204.8* GB/s
Launch Price
$1,350*
PCI-Express
Gen 4, 128 Lanes (CPU only)*
Process Size
7* nm
Cache L3
32 MB (per die)*
Configurable TDP
180* W
Transistors
15,200 million*
Die Size
4x 74 mm²*
Package
FCLGA-4094*
Market
Server/Workstation*
Production Status
Active*

* Provisional data