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CPU

Unspecified

Core2 Solo ULV SU3500

Processor

CPU cores: 1^*
CPU threads: 1^*
Thermal design power: 5.50 W^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*
CPU threads: 1^*
Base clock: 1.4 GHz^*
Socket / package: BGA956^*
Process node: 45 nm^*

Cache hierarchy

L2^*
Size
3 MB^*
Level
L2^*
Scope
L2 Cache^*

Power specifications

Thermal design power: 5.50 W^*

System configuration

Detailed specifications

Specifications 1 · 15 fields

cache size: 3,072^*
tdp: 5.5^*
socket: BGA956^*
cores: 1^*
vertical segment: Mobile^*
status: Discontinued^*
max temp: 100^*
package size: 22mm x 22mm^*
threads: 1^*
name: Intel Core2 Solo ULV SU3500^*
processor number: SU3500^*
launch date: 2009-05-01^*
lithography: 45^*
bus speed: 800^*
base frequency: 1,400^*

Specifications 2 · 29 fields

Total Cores

1^*

Processor Base Frequency

1.4^* GHz

Cache

3.0^* MB

Scope and conditions

source_native_row_context

Cache description: L2 Cache^*
Original declaration: 3 MB L2 Cache^*

Bus Speed

800^* MHz

FSB Parity

No^*

TDP

5.5^* W

VID Voltage Range

1.050V-1.150V^*

Marketing Status

Discontinued^*

Launch Date

Q2'09^*

Servicing Status

End of Servicing Updates^*

Embedded Options Available

No^*

Sockets Supported

BGA956^*

Package Size

22mm x 22mm^*

Processing Die Size

107 mm2^*

# of Processing Die Transistors

410 million^*

TJUNCTION

100^* °C

Intel® Turbo Boost Technology ‡

No^*

Intel® Hyper-Threading Technology ‡

No^*

Intel® Virtualization Technology (VT-x) ‡

Yes^*

Intel® 64 ‡

Yes^*

Instruction Set

64-bit^*

Enhanced Intel SpeedStep® Technology

Yes^*

Intel® Demand Based Switching

No^*

Product Collection

Legacy Intel® Core™ Processors^*

Vertical Segment

Mobile^*

Intel® Trusted Execution Technology ‡

Yes^*

Execute Disable Bit ‡

Yes^*

Processor Number

SU3500^*

Lithography

45^* nm

Specifications 3 · 10 fields

product: Core2 Solo ULV SU3500^*
lith: 45^*
status: Discontinued^*
releaseDate: 2,009^*
cores: 1^*
threads: 1^*
baseClock: 1.4^*
cache: 5.5^*
cacheInfo: L2 Cache^*
TDP: 3^*

* Provisional data