Core 2 Duo T9500

Processor

CPU cores: 2^*
CPU threads: 2^*
Thermal design power: 35 W^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 2^*
CPU threads: 2^*
Base clock: 2.6 GHz^*
CPU reference clock: 200 MHz^*
Socket / package: Socket P^*
Hardware threads per core: 1^*

Power specifications

Thermal design power: 35 W^*

System configuration

Detailed specifications

Specifications 1 · 8 fields

Release: Jan 7th, 2008^*
Name: Core 2 Duo T9500^*
Codename: Penryn^*
Cores: 2^*
Clock: 2.6^* GHz
Socket: Socket P^*
Process: 45^* nm
TDP: 35^* W

Specifications 2 · 41 fields

ifu CPU microarchitecture: 5^*
metal layers Manufacturing process: 9^*
lsfu CPU microarchitecture: 2^*
metal Manufacturing process: copper^*
fpfu CPU microarchitecture: 4^*
gate type Manufacturing process: high k^*
model: T9500^*
date: 2008-01-01^*
clock: 2,600^*
max inst decoded CPU microarchitecture: 5^*
rob size CPU microarchitecture: 96^*
hw nthreadspercore: 1^*
iwindow CPU microarchitecture: 32^*
hw ncores: 2^*
tdp: 35^*
bus width: 64^*
arch int reg CPU microarchitecture: 8,533^*
transistors: 410^*
die size: 107^*
vdd low: 1^*
vdd high: 1.25^*
out of order CPU microarchitecture: t^*
integrated mc CPU microarchitecture: f^*
fanout Process gate-delay observation: 2^*
l1i CPU cache configuration: 32^*
name Processor family: Core 2 Duo^*
name CPU microarchitecture: Core:Penryn^*
name Processor code name: Penryn^*
delay Process gate-delay observation: 5.1^*
isa CPU microarchitecture: x86-64^*
l1d CPU cache configuration: 32^*
l2 shared CPU cache configuration: 6,144^*
vdd Process gate-delay observation: 1.1^*
gate type Process gate-delay observation: inv^*
isa extensions CPU microarchitecture: SSE4.1^*
year Manufacturing process: 2007^*
technology Manufacturing process: CMOS^*
feature size Manufacturing process: 0.045^*
int pipestages CPU microarchitecture: 14^*
channel length Manufacturing process: 0.035^*
max uop issued per cycle CPU microarchitecture: 6^*

Specifications 3 · 32 fields

name: Core 2 Duo T9500^*
Release Date: Jan 7th, 2008^*
Part#: Q4GG Q9WW QZOR SLAQH SLAYX^*
Frequency: 2.6^* GHz
Base Clock: 200^* MHz
Multiplier: 13.0x^*
Multiplier Unlocked: No^*
Voltage: 1.15^* V
TDP: 35^* W
Codename: Penryn^*
Socket: Intel Socket P^*
Generation: Core 2 Duo (Penryn)^*
Memory Support: DDR2, DDR3^*
ECC Memory: No^*
# of Cores: 2^*
# of Threads: 2^*
SMP # CPUs: 1^*
Integrated Graphics: On certain motherboards (Chipset feature)^*
Cache L1: 64 KB (per core)^*
Cache L2: 6 MB (shared)^*
Features: MMX, SSE, SSE2, SSE3, SSSE3, SSE4, SSE4.1, Intel 64, C1E, C2E, EIST, XD bit, VT-x^*
Foundry: Intel^*
Memory Bus: Dual-channel^*
tJMax: 105°C^*
Launch Price: $530^*
Process Size: 45^* nm
Chipsets: GM965, PM965, GS45, GM45, PM45^*
Transistors: 410 million^*
Die Size: 107^* mm²
Package: µFC-PGA8^*
Market: Mobile^*
Production Status: End-of-life^*

* Provisional data

Processing & platform

Power specifications

System configuration

Detailed specifications

Devices using this component