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CPU

Unspecified

Celeron 1.66 GHz, 1M Cache, 667 MHz FSB

Processor

CPU cores: 1^*
CPU threads: 1^*
Thermal design power: 27 W^*

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 1^*
CPU threads: 1^*
Base clock: 1.66 GHz^*
Socket / package: PPGA478^*
Process node: 65 nm^*

Cache hierarchy

L2^*
Size
1 MB^*
Level
L2^*
Scope
L2 Cache^*

Power specifications

Thermal design power: 27 W^*

System configuration

Detailed specifications

Specifications 1 · 14 fields

cache size: 1,024^*
tdp: 27^*
socket: PPGA478^*
cores: 1^*
vertical segment: Desktop^*
status: Discontinued^*
max temp: 100^*
package size: 35mm x 35mm^*
threads: 1^*
name: Intel Celeron 1.66 GHz, 1M Cache, 667 MHz FSB^*
launch date: 2006-02-01^*
lithography: 65^*
bus speed: 667^*
base frequency: 1,660^*

Specifications 2 · 29 fields

Marketing Status

Discontinued^*

Launch Date

Q1'06^*

Embedded Options Available

Yes^*

Servicing Status

End of Servicing Lifetime^*

Sockets Supported

PPGA478^*

TCASE

100^* °C

Package Size

35mm x 35mm^*

Processing Die Size

90 mm2^*

# of Processing Die Transistors

151 million^*

Product Collection

Legacy Intel® Celeron® Processor^*

Intel® Turbo Boost Technology ‡

No^*

Intel® Hyper-Threading Technology ‡

No^*

Intel® 64 ‡

No^*

Instruction Set

32-bit^*

Idle States

Yes^*

Enhanced Intel SpeedStep® Technology

Yes^*

Intel® Demand Based Switching

No^*

Vertical Segment

Desktop^*

Intel® Virtualization Technology (VT-x) ‡

Yes^*

Intel® Trusted Execution Technology ‡

No^*

Execute Disable Bit ‡

Yes^*

Lithography

65^* nm

# of Cores

1^*

Processor Base Frequency

1.66^* GHz

Cache

1.0^* MB

Scope and conditions

source_native_row_context

Cache description: L2 Cache^*
Original declaration: 1 MB L2 Cache^*

Bus Speed

667^* MHz

FSB Parity

No^*

TDP

27^* W

VID Voltage Range

1.1125-1.25V^*

Specifications 3 · 7 fields

product: Celeron 1.66 GHz, 1M Cache, 667 MHz FSB^*
status: Discontinued^*
releaseDate: 2,006^*
cores: 1^*
baseClock: 1.66^*
cache: 1^*
cacheInfo: L2 Cache^*

* Provisional data