GeekRadar / The comparison desk
COMPARE.
CPUAMD Phenom II 910
Processor
- CPU cores
- 4*
Benchmark results
- Reported score · version unreported · score6,381.25*Platform unreported Compare results
- Reported score · version unreported · score24,828.46*Platform unreported Compare results
- Reported score · version unreported · score19,143.75*Platform unreported Compare results
- Reported score · version unreported · score12,774.06*Platform unreported Compare results
Processing & platform
- CPU cores
- 4*
- Hardware threads per core
- 1*
System configuration
Detailed specifications
Specifications · 58 fields
- ifu CPU microarchitecture
- 5*
- lsfu CPU microarchitecture
- 3*
- fpfu CPU microarchitecture
- 3*
- model
- 910*
- date
- 2009-02-01*
- tfu CPU microarchitecture
- 11*
- clock
- 2,600*
- max inst decoded CPU microarchitecture
- 3*
- rob size CPU microarchitecture
- 72*
- hw nthreadspercore
- 1*
- iwindow CPU microarchitecture
- 42*
- hw ncores
- 4*
- bht size CPU microarchitecture
- 16,384*
- tdp
- 95*
- btb size CPU microarchitecture
- 2,048*
- bus width
- 64*
- arch int reg CPU microarchitecture
- 96*
- transistors
- 758*
- arch fp reg CPU microarchitecture
- 96*
- die size
- 258*
- total arch reg CPU microarchitecture
- 96*
- vdd low
- 0.875*
- vdd high
- 1.425*
- out of order CPU microarchitecture
- t*
- integrated mc CPU microarchitecture
- t*
- l1i CPU cache configuration
- 64*
- name CPU microarchitecture
- K10*
- name Processor family
- Phenom II*
- name Processor code name
- Deneb*
- isa CPU microarchitecture
- x86-64*
- l1d CPU cache configuration
- 64*
- l2 shared CPU cache configuration
- 512*
- score CoreMark observation
- 12,774.06*
- score CoreMark observation
- 24,828.46*
- score CoreMark observation
- 6,381.25*
- score CoreMark observation
- 19,143.75*
- isa extensions CPU microarchitecture
- SSE4a*
- l2 shared ncores CPU cache configuration
- 1*
- threads CoreMark observation
- 2*
- threads CoreMark observation
- 4*
- threads CoreMark observation
- 3*
- threads CoreMark observation
- 1*
- year Manufacturing process
- 2007*
- fp pipestages CPU microarchitecture
- 17*
- l3 shared CPU cache configuration
- 6,144*
- technology Manufacturing process
- CMOS*
- thread model CoreMark observation
- PThreads*
- thread model CoreMark observation
- Pthreads*
- thread model CoreMark observation
- Pthreads*
- thread model CoreMark observation
- PThreads*
- date CoreMark observation
- 2009-07-13*
- date CoreMark observation
- 2009-07-13*
- date CoreMark observation
- 2009-07-13*
- date CoreMark observation
- 2009-07-13*
- feature size Manufacturing process
- 0.045*
- int pipestages CPU microarchitecture
- 12*
- channel length Manufacturing process
- 0.025*
- max uop issued per cycle CPU microarchitecture
- 9*
0 selected Compare 0
* Provisional data