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CPU

AMD

AMD EPYC 9254

Processor Released Nov 10, 2022

CPU cores: 24
CPU threads: 48
Maximum boost clock: 4.15 GHz
Thermal design power: 220 W

No matched benchmark results are available for this entry yet.

Processing & platform

CPU cores: 24
CPU threads: 48
Base clock: 2.9 GHz
Maximum boost clock: 4.15 GHz
L3 cache: 128 MB
L2 cache: 24 MB
Socket / package: SP5

Cache hierarchy

L1 / total
Level
L1
Scope
total
Size
1.5 MB
L2 / total
Level
L2
Scope
total
Size
24 MB
L3 / total
Level
L3
Scope
total
Size
128 MB

Compatible sockets

Memory & storage

Memory channels: 12

Supported memory

DDR5-4800
Technology
DDR5
Transfer rate
4,800 MT/s

CPU memory support

DDR5
Variant / details
Up to 4800 MT/s
Technology
DDR5
Transfer rate
4,800 MT/s
Per-socket memory bandwidth
Variant / details
460.8 GB/s

Power specifications

Thermal design power: 220 W

CPU power specifications

Configurable TDP 200–240 W
Maximum rating
240 W
Minimum rating
200 W
Power specification
Configurable TDP
Variant / details
200-240W

System configuration

Detailed specifications

Specifications 1 · 11 fields

Maximum turbo frequency

4.15^* GHz

Scope and conditions

native_context

Clock scope: Maximum turbo declaration; not measured or sustained all-core frequency^*

Codename

Genoa^*

Processor model

EPYC 9254^*

Full processor designation

AMD EPYC 9254 24-Core Processor^*

Processor family

AMD EPYC^*

Launch year

precision: year^*
text: 2022^*

Declared memory capacity

6^* TB

Scope and conditions

native_context

Capacity unit base: Not independently established^*

CPU cores

24^*

L3 cache

128^* MB

Scope and conditions

native_context

Capacity unit base: Not independently established^*

Thermal design power declaration

200^* W

CPU threads

48^*

Specifications 2 · 23 fields

# of CPU Cores

24^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

# of Threads

48^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

1kU Pricing

2,299 USD^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

All Core Boost Speed

3.9GHz^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

AMD Configurable TDP (cTDP)

200-240W^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Base Clock

2.9GHz^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

CPU Socket

SP5^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Default TDP

200W^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Family

AMD EPYC™^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

L3 Cache

128MB^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Line

AMD EPYC™ 9004 Series^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Max. Boost Clock ¹ ²

Up to 4.15GHz^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Memory Channels

12^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Model

AMD EPYC™ 9254^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

PCI Express® Version

PCIe 5.0 x128^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Per Socket Mem BW

460.80 GB/s^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Platform

Server^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Product ID Tray

100-000000480^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Socket Count

1P/2P^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Supported Technologies

AMD Infinity Guard, AMD Infinity Architecture^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

System Memory Specification

Up to 4800MHz^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

System Memory Type

DDR5^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

Workload Affinity

General Purpose, GPU/FPGA Accelerated, Per core CAE/CFD/FEA, SW-defined storage^*

Scope and conditions

native_context

member: amd-cpus.csv^*
row: 359^*

* Provisional data