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CPU

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PowerQUICC

Processore

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Configurazione di sistema

Specifiche dettagliate

Specifiche · 6 campi

Famiglia di processori per comunicazioni

Designer: Freescale Semiconductor^*
Instruction families: PowerPC^*
Power ISA^*
Applications: Networking^*
Automotive^*
Industrial^*
Storage^*
Printing^*
Consumer electronics^*
Communications engine: Separate QUICC/CPM RISC core; implementation varies^*

Implementazioni PowerQUICC III

Model
MPC8540^*
Core
e500v1^*
Clock endpoints
Minimum
600^* MHz
Maximum
1^* GHz
Gigabit Ethernet controllers
2^*
RapidIO
Sì^*
Model
MPC8544E^*
Core
e500v2^*
Process
90^* nm
Model
MPC8569E^*
Core
e500v2^*
Clock
1,33^* GHz
Process
45^* nm
Communications engine
Enhanced QUICC Engine^*
Model
MPC8572E^*
Cores
2^*
Core
e500v2^*
Maximum clock
1,5^* GHz

PowerQUICC I / MPC8xx

Pipeline stages

4^*

Issue width

1^*

Maximum family clock

133^* MHz

L1 cache variants

1^* – 16^* KiB

Named implementations

Model
MPC821^*
Introduced
1.995^*
Maximum clock
50^* MHz
FPU
No^*
Model
MPC860^*
Introduced
1.995^*
Maximum clock
80^* MHz
Communications engine
QUICC^*
Model
MPC850^*
Introduced
1.997^*
Maximum clock
50^* MHz
Integrated interfaces
- USB^*
- Ethernet^*

PowerQUICC II / MPC82xx

Introduced: 1.998^*
Core: PowerPC 603e / G2^*
L1 instruction: 16^* KiB
L1 data: 16^* KiB
Maximum family clock: 450^* MHz

PowerQUICC II Pro / MPC83xx

Introduced: 2.004^*
Core: PowerPC e300^*
L1 instruction: 32^* KiB
L1 data: 32^* KiB
Reported clock ceiling: 677^* MHz
Memory types: DDR SDRAM^*
DDR2 SDRAM^*
Communications engine: QUICC Engine; absent on 834x variants^*
Encryption suffix: E^*

PowerQUICC III / MPC85xx

Introduced

2.003^*

Core family

PowerPC e500^*

Word size

32^* bit

Pipeline stages

7^*

Issue width

2^*

L1 instruction

32^* KiB

L1 data

32^* KiB

Clock endpoints

Minimum: 533^* MHz
Maximum: 1,5^* GHz

Memory types

DDR^*
DDR2^*

Communications engine

CPM, QUICC Engine or absent, depending on model^*

Encryption suffix

E^*

* Dati provvisori