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CPU
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AT&T Hobbit

Processore

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Configurazione di sistema

Specifiche dettagliate

Specifiche · 5 campi
Prezzo iniziale in volume annunciato nel 1992
Model
92010*
Unit price
35* USD
Order quantity
10.000*
Period
1.992*
Scope
Historical announcement; not a current offer*
Famiglia di processori
Designer
AT&T*
Architecture lineage
CRISP / C Machine*
Introduced
1.992*
Project ended
1994-03*
Primary design target
Code compiled from C*
Architettura della cache dello stack
Execution model
Memory-to-memory*
Stack-cache entries
64*
Entry width
32* bit
Access
Stack-relative*
Directly accessible general-purpose registers
No*
Ruoli dei chip complementari
92011
System Management Unit*
92012
PCMCIA Controller*
92013
Peripheral Controller*
92014
Display Controller*
92021M
System Management Unit*
92021MX
System Management Unit*
92024M
Display Controller*
Configurazioni dei processori
  • Model
    92010*
    Introduced
    1.992*
    Supply voltage
    3,3* V
    Instruction cache
    3* KB
    Reported performance ceiling
    13,5* VAX MIPS
    Workload/version
    Not specified*
  • Model
    92020S*
    Introduced
    1.993*
    Pin-compatible model
    92010*
    Instruction cache
    6* KB
    Typical power
    210* mW
    Reported performance
    16* VAX MIPS
    Workload/version
    Not specified*
  • Model
    92020M*
    Instruction cache
    6* KB
    Bus
    Multiplexed address/data*
  • Model
    92020MX*
    Instruction cache
    3* KB
    PCMCIA channels
    1*
    Maximum display matrix
    Width
    640*
    Height
    480*
    Unit
    pixels*

* Dati provvisori